Telecommunication networks of time division switches, interconnected by digital transmission are being put into place. At each switch, each incoming bit stream is brought into its own buffer. Then the clock in the switch reads each buffer to re-establish phase. Care must be taken to keep frequency differences between various clocks from becoming too large. Based on empirically defined data transmission requirements, one major network has determined that fractional frequency inequality between switches should be no worse than 1.7 X 10 to the minus 9 power. A network needs near frequency equality between its own switches, and also between its switches and other networks with which it interfaces. As a practical matter, the best way to achieve needed frequency equality is for each network to have master clock with an accuracy which is at least as good as 1 X 10 to the minus 10 power. The relationship between the master and the secondary clock is discussed. The questions of master clock accuracy and precision and the free-running capability of the secondary clocks are examined.